The present invention relates generally to semiconductor device manufacturing and, more particularly, to an interface structure for channel mobility improvement in high-k metal gate stacks.
In standard complementary metal oxide semiconductor (CMOS) devices, polysilicon is typically used as the gate material. The technology of fabricating CMOS devices using polysilicon gates has been in a constant state of development, and is now widely used in the semiconductor industry. One advantage of using polysilicon gates is that they can sustain high temperatures. However, there are also some problems associated with using a polysilicon gate. For example, due to the poly-depletion effect, polysilicon gates commonly used in CMOS devices are becoming a gating factor in chip performance for channel lengths of 0.1 micron and below. Another problem with polysilicon gates is that the dopant material in the polysilicon gate (e.g., boron) can easily diffuse through the thin gate dielectric, causing further degradation of the device performance. Thus, one proposed way of improving the performance of sub-micron transistors is to use metal gates in place of conventional polysilicon gates, particularly with the advent of high-k gate dielectric materials.
While replacing traditional polysilicon gates with metal or metal alloy gate electrodes eliminates the polysilicon depletion effect, there are problems associated with the use of metal gates and high-k gate dielectric including, for example, high threshold voltage (Vt) due to Fermi-level pinning effect. The threshold voltage is the gate voltage value required to render the channel conductive by formation of an inversion layer at the surface of the semiconductor channel. For enhancement-mode (e.g., normally off) devices, Vt is positive for NFET devices and negative for PFET devices. The threshold voltage is dependent upon the flat-band voltage, which in turn depends on the work function difference between the gate and the substrate materials, as well as on surface charge.
The work function of a material is a measure of the energy required to move an electron in the material outside of a material atom from the Fermi level, and is usually expressed in electron volts (eV). For CMOS devices, it is desirable to provide stable threshold voltages for the NFETs and PFETs. To establish Vt values, the work functions of the NFET and PFET gate contact and the corresponding channel materials are independently tuned or adjusted. Such work function values may be, for example, about 4.1 and 5.2 electron volts (eV) for the n-and p-channel electrodes, respectively. Accordingly, gate stack engineering is employed to adjust the work function of the gate contact materials, where different gate work function values are established for NFET and PFET gates.